133 lines
4.8 KiB
Markdown
133 lines
4.8 KiB
Markdown
# XD84
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Development docs covering the following:
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- Kimera core
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- RGB
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- Backlight
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## Kimera core
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What little available info that was available for the qmk port
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- atmega32u4 16Mhz
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- board seems to have a 6Mhz crystal
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- 2x PCA9555 I2C IO expander
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Links:
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- [Schematic, BOM, Gerbers](/kairyu/kimera/blob/master/kimera_core)
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- [Original firmware](https://github.com/kairyu/tmk_keyboard_custom/tree/master/keyboard/kimera)
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```c
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/*
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Kimera_core_v1.0 Components
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U1 (atmega32u4)
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,----------------.
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TX --| TX0(PD3) RAW |--
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RX --| RX1(PD2) GND |--
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--| GND RESET |-- RST
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--| GND VCC |--
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SDA --| 2(PD1) (PF4)A3 |--
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SCL --| 3(PD0) (PF5)A2 |--
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(INT) --| 4(PD4) (PF6)A1 |--
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--| 5(PC6) (PF7)A0 |--
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--| 6(PD7) (PB1)15 |-- SCK
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LED2 --| 7(PE6) (PB3)14 |-- MISO
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LED1 --| 8(PB4) (PB2)16 |-- MOSI
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LED3 --| 9(PB5) (PB6)10 |-- LED4
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`----------------'
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IC1 (PCA9555) IC2 (PCA9555)
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,----------. ,----------.
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SDA --| SDA P00 |-- P1 SDA --| SDA P00 |-- P17
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SCL --| SCL P01 |-- P2 SCL --| SCL P01 |-- P18
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INT --| INT P02 |-- P3 INT --| INT P02 |-- P19
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| P03 |-- P4 | P03 |-- P20
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GND --| A0 P04 |-- P5 VCC --| A0 P04 |-- P21
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SJ1 --| A1 P05 |-- P6 SJ1 --| A1 P05 |-- P22
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SJ2 --| A2 P06 |-- P7 SJ2 --| A2 P06 |-- P23
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| P07 |-- P8 | P07 |-- P24
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| | | |
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| P10 |-- P9 | P10 |-- P25
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| P11 |-- P10 | P11 |-- P26
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| P12 |-- P11 | P12 |-- P27
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| P13 |-- P12 | P13 |-- P28
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| P14 |-- P13 | P14 |-- P29
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| P15 |-- P14 | P15 |-- P30
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| P16 |-- P15 | P16 |-- P31
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| P17 |-- P16 | P17 |-- P32
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`----------' `----------'
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*/
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```
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### Bootloader
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Default bootloader is `atmel-dfu`.
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Reboot to bootloader via magnetic switch next to icsp header.
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Flash using regular dfu methods.
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### XD84 pin mappings
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Taken from [kimera-config.json](https://github.com/kairyu/tkg/blob/master/keyboard/config/kimera-config.json)
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"row_mapping": [ 1, 2, 3, 4, 5, 6 ],
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"col_mapping": [ 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ],
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# RGB
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- PIN C7
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- Number of RGB LED 7
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# Backlight
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TODO - not working
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## Assumptions
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### Pin/Port mappings
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- All cols are on the same IC
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- All rows are on the same IC and port
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- Pins mapped sequentially
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- Each port only does row or column not a mixture of both
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- No need to have complex port config
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-
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| ROW index | Kimera Pin | PCA9555 |
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| ----------|------------|-------------------|
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| 0 | 1 | IC1 Port 0 pin 0 |
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| 1 | 2 | IC1 Port 0 pin 1 |
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| 2 | 3 | IC1 Port 0 pin 2 |
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| 3 | 4 | IC1 Port 0 pin 3 |
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| 4 | 5 | IC1 Port 0 pin 4 |
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| 5 | 6 | IC1 Port 0 pin 5 |
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- Safe enough to assume `row_index == pin`
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| COL index | Kimera Pin | PCA9555 |
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| ----------|------------|-------------------|
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| 0 | 17 | IC2 Port 0 pin 0 |
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| 1 | 18 | IC2 Port 0 pin 1 |
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| 2 | 19 | IC2 Port 0 pin 2 |
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| 3 | 20 | IC2 Port 0 pin 3 |
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| 4 | 21 | IC2 Port 0 pin 4 |
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| 5 | 22 | IC2 Port 0 pin 5 |
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| 6 | 23 | IC2 Port 0 pin 6 |
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| 7 | 24 | IC2 Port 0 pin 7 |
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| 8 | 25 | IC2 Port 1 pin 0 |
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| 9 | 26 | IC2 Port 1 pin 1 |
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| 10 | 27 | IC2 Port 1 pin 2 |
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| 11 | 28 | IC2 Port 1 pin 3 |
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| 12 | 29 | IC2 Port 1 pin 4 |
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| 13 | 30 | IC2 Port 1 pin 5 |
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| 14 | 31 | IC2 Port 1 pin 6 |
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- Safe enough to assume here col_index does not need to be converted to pin
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- Reading both ports one after the other gives us the same sequential behavior
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- maps to the usual practice of reading matrix columns
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- while this technically gives 16 column reads, the 16th column can never be set so is safely ignored
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## Notes
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[pca9555 datasheet](https://www.ti.com/lit/ds/symlink/pca9555.pdf)
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- Other Kimera based boards with non sequential pin mappings, pins mapped across ICs, or mixed row/col configs will need more complicated `pin -> i2c_addr,port,pin` logic as well as rather more complex pin functions.
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## Return to stock firmware
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Not tested but original firmware seems to be available in the [kairyu/tkg-firmware](https://github.com/kairyu/tkg-firmware/blob/master/kimera-core.hex) repo.
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